According to Moore's Law, the historical trend of the semiconductor industry, the level of complexity of semiconductor devices doubles every eighteen months. The size of the smallest structure in a semiconductor device now is 70% the size of the smallest structure three years ago. As structure size shrinks, chips become more densely populated permitting faster and more powerful machines. The aim of engineers within the semiconductor industry is to constantly find ways to pack more structures on each chip while maintaining fabrication process robustness and keeping the consumer cost per function to a minimum.
One set of the hundreds of steps in the semiconductor wafer fabrication process for flash memory devices is devoted to the definition of the first polysilicon, or “poly-1” layer above the substrate 101 (shown in FIG. 1). FIG. 1 is a cross-sectional view of a semiconductor wafer in one stage of the fabrication process. Before the deposition of the poly-1 layer, trenches 103 are formed in the substrate. Trench etch into silicon substrate 101 is performed through conventional methods by depositing a layer of barrier oxide and a nitride layer (ON) 102 is used as an etch mask.
Following trench formation, the trenches are over-filled with a dielectric oxide material 106, or “field oxide,” as shown in FIG. 2. As illustrated in FIG. 3, the wafer is then polished by a Chemical Mechanical Polish, or Chemical Mechanical Planarization (CMP) process 107 to remove the excess field oxide from on top of the nitride layer 102. The effect of CMP 107 is depicted in FIG. 4. Then, the nitride layer 102 is stripped with an etch or polish process 108, shown in FIG. 5. It is important that after the nitride strip, the remaining field oxide trench-fills form mesas 109 which protrude from the substrate, as shown in FIG. 6. The height of these mesas 109 is determined by the thickness 118 of the nitride layer of the ON mask 102. Using a conventional method, the thickness of the nitride layer is approximately 700-1500 angstroms.
Filled trenches may be used to isolate devices from each other in the core 104, a technique known as Shallow Trench Isolation (STI). STI has emerged as the primary technique for device isolation for advanced Ultra Large Scale Integration (ULSI) Complimentary Metal-Oxide-Semiconductor (CMOS) technologies. Filled trenches may also be utilized in the periphery 105 for the active transistor isolation.
The next step in the conventional method is poly-1 110 deposition, shown in FIG. 7, followed by poly-1 definition. The definition of the poly-1 layer is complicated by two factors. The first of these factors is that in the core 104, the mesas of trench-fill oxides 109 must not be covered by polysilicon 110, while the mesas of trench-fill oxides in the periphery 117 must be covered by a layer of polysilicon 110 of a certain thickness 116, as shown in FIG. 8.
In order to achieve proper poly-1 definition, the conventional method employs a mask and etch process. As FIG. 8 depicts, a mask 111 is lithographically applied to the top of the poly-1 layer 110. FIG. 9 illustrates how in the conventional method, once the poly-1 definition mask 111 is applied, an etch 113 is performed to remove polysilicon 110 from on top of the core mesas 109, as shown in FIG. 10. A stripping process 115, shown in FIG. 11, is then employed to remove the poly-1 definition mask 111. Once the poly 1 definition mask 111 is removed, as shown in FIG. 12, the poly-1 layer 110 is properly defined and the wafer proceeds to the rest of the fabrication process.
Proper alignment of the poly-1 definition mask is imperative. A misalignment of the poly-1 definition mask could result in portions of the poly-1 layer overlapping onto sensitive areas, which could compromise the optimum functioning of the chips, or perhaps render the entire wafer useless.